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<H1>Intel 80386 Reference Programmer's Manual<BR>
Table of Contents</H2>
<H3><A HREF="c01.htm">Chapter 1 -- Introduction to the 80386</A></H3>
<UL>
<LI> <A HREF="s01_01.htm">1.1 Organization of This Manual</A>
<LI> <A HREF="s01_02.htm">1.2 Related Literature</A>
<LI> <A HREF="s01_03.htm">1.3  Notational Conventions</A>
</UL>
<H2><A HREF="PI.htm">Part I Applications Programming</A></H2>
<H3><A HREF="c02.htm">Chapter 2 -- Basic Programming Model</A></H3>
<UL>
<LI> <A HREF="s02_01.htm">2.1 Memory Organization and Segmentation</A><BR>
<LI> <A HREF="s02_02.htm">2.2 Data Types</A><BR>
<LI> <A HREF="s02_03.htm">2.3 Registers</A><BR>
<LI> <A HREF="s02_04.htm">2.4 Instruction Format</A><BR>
<LI> <A HREF="s02_05.htm">2.5 Operand Selection</A><BR>
<LI> <A HREF="s02_06.htm">2.6  Interrupts and Exceptions</A>
</UL>
<H3><A HREF="c03.htm">Chapter 3 -- Applications Instruction Set</A></H3>
<UL>
<LI> <A HREF="s03_01.htm">3.1 Data Movement Instructions</A><BR>
<LI> <A HREF="s03_02.htm">3.2 Binary Arithmetic Instructions</A><BR>
<LI> <A HREF="s03_03.htm">3.3 Decimal Arithmetic Instructions</A><BR>
<LI> <A HREF="s03_04.htm">3.4 Logical Instructions</A><BR>
<LI> <A HREF="s03_05.htm">3.5 Control Transfer Instructions</A><BR>
<LI> <A HREF="s03_06.htm">3.6 String and Character Translation Instructions</A><BR>
<LI> <A HREF="s03_07.htm">3.7 Instructions for Block-Structured Languages</A><BR>
<LI> <A HREF="s03_08.htm">3.8 Flag Control Instructions</A><BR>
<LI> <A HREF="s03_09.htm">3.9 Coprocessor Interface Instructions</A><BR>
<LI> <A HREF="s03_10.htm">3.10 Segment Register Instructions</A><BR>
<LI> <A HREF="s03_11.htm">3.11  Miscellaneous Instructions</A>
</UL>
<H2><A HREF="PII.htm">Part II Systems Programming</A></H2>
<H3><A HREF="c04.htm">Chapter 4 -- Systems Architecture</A></H3>
<UL>
<LI> <A HREF="s04_01.htm">4.1 Systems Registers</A><BR>
<LI> <A HREF="s04_02.htm">4.2  Systems Instructions</A>
</UL>
<H3> <A HREF="c05.htm">Chapter 5 -- Memory Management</A></H3>
<UL>
<LI> <A HREF="s05_01.htm">5.1 Segment Translation</A><BR>
<LI> <A HREF="s05_02.htm">5.2 Page Translation</A><BR>
<LI><A HREF="s05_03.htm">5.3  Combining Segment and Page Translation</A>
</UL>
<H3><A HREF="c06.htm">Chapter 6 -- Protection</A></H3>
<UL>
<LI> <A HREF="s06_01.htm">6.1 Why Protection?</A><BR>
<LI> <A HREF="s06_02.htm">6.2 Overview of 80386 Protection Mechanisms</A><BR>
<LI> <A HREF="s06_03.htm">6.3 Segment-Level Protection</A><BR>
<LI> <A HREF="s06_04.htm">6.4 Page-Level Protection</A><BR>
<LI> <A HREF="s06_05.htm">6.5  Combining Page and Segment Protection</A>
</UL>
<H3> <A HREF="c07.htm">Chapter 7 -- Multitasking</A></H3>
<UL>
<LI> <A HREF="s07_01.htm">7.1 Task State Segment</A><BR>
<LI> <A HREF="s07_02.htm">7.2 TSS Descriptor</A><BR>
<LI> <A HREF="s07_03.htm">7.3 Task Register</A><BR>
<LI> <A HREF="s07_04.htm">7.4 Task Gate Descriptor</A><BR>
<LI> <A HREF="s07_05.htm">7.5 Task Switching</A><BR>
<LI> <A HREF="s07_06.htm">7.6 Task Linking</A><BR>
<LI> <A HREF="s07_07.htm">7.7  Task Address Space</A>
</UL>
<H3><A HREF="c08.htm">Chapter 8 -- Input/Output</A></H3>
<UL>
<LI> <A HREF="s08_01.htm">8.1 I/O Addressing</A><BR>
<LI> <A HREF="s08_02.htm">8.2 I/O Instructions</A><BR>
<LI> <A HREF="s08_03.htm">8.3  Protection and I/O</A>
</UL>
<H3><A HREF="c09.htm">Chapter 9 -- Exceptions and Interrupts</A></H3>
<UL>
<LI> <A HREF="s09_01.htm">9.1 Identifying Interrupts</A><BR>
<LI> <A HREF="s09_02.htm">9.2 Enabling and Disabling Interrupts</A><BR>
<LI> <A HREF="s09_03.htm">9.3 Priority Among Simultaneous Interrupts and Exceptions</A><BR>
<LI> <A HREF="s09_04.htm">9.4 Interrupt Descriptor Table</A><BR>
<LI> <A HREF="s09_05.htm">9.5 IDT Descriptors</A><BR>
<LI> <A HREF="s09_06.htm">9.6 Interrupt Tasks and Interrupt Procedures</A><BR>
<LI> <A HREF="s09_07.htm">9.7 Error Code</A><BR>
<LI> <A HREF="s09_08.htm">9.8 Exception Conditions</A><BR>
<LI> <A HREF="s09_09.htm">9.9 Exception Summary</A><BR>
<LI> <A HREF="s09_10.htm">9.10  Error Code Summary</A>
</UL>
<H3><A HREF="c10.htm">Chapter 10 -- Initialization</A></H3>
<UL>
<LI> <A HREF="s10_01.htm">10.1 Processor State After Reset</A><BR>
<LI> <A HREF="s10_02.htm">10.2 Software Initialization for Real-Address Mode</A><BR>
<LI> <A HREF="s10_03.htm">10.3 Switching to Protected Mode</A><BR>
<LI> <A HREF="s10_04.htm">10.4 Software Initialization for Protected Mode</A><BR>
<LI> <A HREF="s10_05.htm">10.5 Initialization Example</A><BR>
<LI> <A HREF="s10_06.htm">10.6  TLB Testing</A>
</UL>
<H3><A HREF="c11.htm">Chapter 11 -- Coprocessing and Multiprocessing</A></H3>
<UL>
<LI> <A HREF="s11_01.htm">11.1 Coprocessing</A><BR>
<LI> <A HREF="s11_02.htm">11.2  General Multiprocessing</A>
</UL>
<H3><A HREF="c12.htm">Chapter 12 -- Debugging</A></H3>
<UL>
<LI> <A HREF="s12_01.htm">12.1 Debugging Features of the Architecture</A><BR>
<LI> <A HREF="s12_02.htm">12.2 Debug Registers</A><BR>
<LI> <A HREF="s12_03.htm">12.3  Debug Exceptions</A>
</UL>
<H2><A HREF="PIII.htm">Part III Compatibility</A></H2>
<H3><A HREF="c13.htm">Chapter 13 -- Executing 80286 Protected-Mode Code</A></H3>
<UL> 
<LI> <A HREF="s13_01.htm">13.1 80286 Code Executes as a Subset of the 80386</A>
<LI> <A HREF="s13_02.htm">13.2 Two ways to Execute 80286 Tasks</A><BR>
<LI> <A HREF="s13_03.htm">13.3  Differences From 80286</A>
</UL>
<H3><A HREF="c14.htm">Chapter 14 -- 80386 Real-Address Mode</A></H3>
<UL>
<LI> <A HREF="s14_01.htm">14.1 Physical Address Formation</A><BR>
<LI> <A HREF="s14_02.htm">14.2 Registers and Instructions</A><BR>
<LI> <A HREF="s14_03.htm">14.3 Interrupt and Exception Handling</A><BR>
<LI> <A HREF="s14_04.htm">14.4 Entering and Leaving Real-Address Mode</A><BR>
<LI> <A HREF="s14_05.htm">14.5 Switching Back to Real-Address Mode</A><BR>
<LI> <A HREF="s14_06.htm">14.6 Real-Address Mode Exceptions</A><BR>
<LI> <A HREF="s14_07.htm">14.7 Differences From 8086</A><BR>
<LI> <A HREF="s14_08.htm">14.8  Differences From 80286 Real-Address Mode</A>
</UL> 
<H3><A HREF="c15.htm">Chapter 15 -- Virtual 8086 Mode</A></H3>
<UL>
<LI> <A HREF="s15_01.htm">15.1 Executing 8086 Code</A><BR>
<LI> <A HREF="s15_02.htm">15.2 Structure of a V86 Task</A><BR>
<LI> <A HREF="s15_03.htm">15.3 Entering and Leaving V86 Mode</A><BR>
<LI> <A HREF="s15_04.htm">15.4 Additional Sensitive Instructions</A><BR>
<LI> <A HREF="s15_05.htm">15.5 Virtual I/O</A><BR>
<LI> <A HREF="s15_06.htm">15.6 Differences From 8086</A><BR>
<LI> <A HREF="s15_07.htm">15.7  Differences From 80286 Real-Address Mode</A>
</UL>
<H3><A HREF="c16.htm">Chapter 16 -- Mixing 16-Bit and 32 Bit Code</A></H3>
<UL>
<LI> <A HREF="s16_01.htm">16.1 How the 80386 Implements 16-Bit and 32-Bit Features</A><BR>
<LI> <A HREF="s16_02.htm">16.2 Mixing 32-Bit and 16-Bit Operations</A><BR>
<LI> 
<A HREF="s16_03.htm">16.3  Sharing Data Segments Among Mixed Code Segments</A>
<LI> <A HREF="s16_04.htm">
16.4  Transferring Control Among Mixed Code Segments></A>
</UL>
<H2><A HREF="PIV.htm">Part IV Instructions Set</A></H2>
<H3><A HREF="c17.htm">Chapter 17 -- 80386 Instruction Set</A></H3>
<UL>
<LI> <A HREF="s17_01.htm">17.1  Operand-Size and Address-Size Attributes</A>
<LI> <A HREF="s17_02.htm">17.2 Instruction Format</A>
</UL>
<H2><A HREF="app.htm">Appendices</A></H2>
<UL>
<LI>
<A HREF="appa.htm">Appendix A -- Opcode Map</A><BR>
<LI>
<A HREF="appb.htm">Appendix B -- Complete Flag Cross-Reference</A><BR>
<LI>
<A HREF="appc.htm">Appendix C -- Status Flag Summary</A><BR>
<LI>
<A HREF="appd.htm">Appendix D -- Condition Codes</A>
</UL>
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